Packaging requirements for semiconductor devices have become more stringent as the competing demands of increased functionality and smaller electronic products continue to force device manufacturers to create ever more complex package designs. In particular, increased demands for compact devices have led package manufacturers to pursue vertical integration of multiple chips to decrease the overall package size, permitting smaller final electronic products.
For example “system-in-package” designs have been created for CMOS image sensors with associated digital signal processor and memory chips. In order to electrically interconnect the chips in these vertically integrated packages, various techniques have been adopted. Conventionally, through-silicon-vias (TSVs) have been formed through silicon chips and filled with conductors that connect to solder bumps positioned beneath each chip.
To eliminate the need for TSVs, the SHELLCASE® (Tessera) technique has been created. In the SHELLCASE technology, electrical leads are formed on the edge of each device chip to interconnect the bonding pad to solder bumps positioned beneath each chip.
Both the TSV and SHELLCASE approaches require expensive wafer processing to create the final multi-chip device package. Further, each solder bump and its associated metallization requires approximately 100 microns of height, placing a lower limit on the final package thickness. Further, the SHELLCASE approach requires a complex electrical path which can lead to decreased package reliability, particularly in view of the large differences in coefficients of thermal expansion between metallization layers and underlying semiconductor materials.
Thus there is a need in the art for improved packaging formed at the wafer level with easy-to-fabricate electrical connections that minimize package thickness and provide reliable interconnections.